Field effect circuits are used mainly in digital applications, whereas for analogue applications, such as in radio signal processing, bipolar circuits are more suitable. There is a need in certain applications, e.g. telephony, for the processing of both digital and analogue signals and this generally requires the provision of two circuit chips each with its associated peripheral circuitry. Many attempts have been made to combine bipolar and MOS technologies on the same chip but to date none has been entirely successful. A commonly used approach is to add a CMOS capability to a SBC (Standard Buried Collector) bipolar technology. This results in a device with high bipolar performance but poor CMOS capability. If bipolar devices are added to good CMOS technology the resulting triply diffused structures have high parasitic resistances and hence poor bipolar performance.
The object of this invention is to minimise or to overcome this disadvantage.
"Our co-pending U.S. patent application Ser. No. 133,269, filed Dec. 16, 1987, which is a continuation of U.S. patent application Ser. No. 83,685, filed Mar. 6, 1986 (corresponding to United Kingdom application No. 8603322) relates" construction that is compatible with CMOS processing and to a process for fabricating the bipolar transistor. Whilst that process is adequate for providing good devices we have now round that yield may be increased by the use of an alternative process.